IP Facts - 2.1 English

AXI Register Slice LogiCORE IP Product Guide (PG373)

Document ID
Release Date
2.1 English
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 UltraScale+, UltraScale, Zynq®-7000 SoC, 7 series
Supported User Interfaces AXI4, AXI4-Lite, AXI3
Resources Performance and Resource Use web page
Provided with Core
Design Files Verilog and VHDL
Example Design Not Provided
Test Bench Not Provided
Constraints File Xilinx Design Constraints (XDC)
Simulation Model Not Provided
Supported S/W Driver N/A
Tested Design Flows 2
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Release Notes and Known Issues N/A
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado® IP catalog.
  2. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide.