Introduction - 2.1 English

AXI Register Slice LogiCORE IP Product Guide (PG373)

Document ID
PG373
Release Date
2020-12-04
Version
2.1 English
Revision

The AXI Register Slice core connects one AXI memory-mapped master to one AXI memory-mapped slave through a set of pipeline registers, typically to break a critical timing path. Several configuration options are available to best suit the nature of the pathway being pipelined.