Multi SLR Crossing - 2.1 English

AXI Register Slice LogiCORE IP Product Guide (PG373)

Document ID
PG373
Release Date
2020-12-04
Version
2.1 English
Revision

This supports spanning zero or more SLR boundaries using a single AXI Register Slice instance. Also, provides a selectable number of intermediate pipeline stages within each SLR to help close timing. All SLR crossings within the core are flop-to-flop with fanout = 1. See Constraining the Core section in the Related Information for floorplanning guidance.

Multi SLR Crossing mode drives registered payload outputs and registered VALID and READY handshake outputs as shown in the figure. The submodule instance names shown can be used in cell-name patterns when writing floorplanning (Pblock) constraints, as needed, to enforce proper SLR placement.

Figure 1. Multi SLR Crossing AXI Register Slice Diagram

The figure shows that the Multi SLR Crossing mode introduces a variable number of latency cycles, as determined by the various SLR Crossing parameters, but no bubble cycles.

Figure 2. Multi SLR Crossing Mode Timing Diagram