Performance - 2.1 English

AXI Register Slice LogiCORE IP Product Guide (PG373)

Document ID
PG373
Release Date
2020-12-04
Version
2.1 English
Revision

For full details about performance and resource use, visit the Performance and Resource Use web page.

Latency

FULLY_REGISTERED Register Slices (each applicable channel)
One latency cycle with no bubble cycles (best-case 100% channel bandwidth).
LIGHT_WEIGHT Register Slices (each applicable channel)
One latency cycle with one bubble cycle (best-case 50% channel bandwidth), which is appropriate for AW, AR, and B channel transfers, and all transfers involving AXI4-Lite endpoints.
SI Reg or MI Reg
One latency cycle, no bubble cycles.
SLR Crossing Mode and SLR TDM Crossing Mode
Three latency cycles (of aclk), no bubble cycles.
Multi SLR Crossing
Overall latency varies between 1 and 17 cycles depending on the number of SLR boundaries crossed and the number of pipeline stages configured within each SLR region.