Registered Input - 2.1 English

AXI Register Slice LogiCORE IP Product Guide (PG373)

Document ID
PG373
Release Date
2020-12-04
Version
2.1 English
Revision

This mode is selected as SI Reg on forward-propagating channels and as MI Reg on response channels. Implemented as a 4-deep FIFO buffer, this mode passes the VALID handshake input and all payload inputs on the source side through simple flip-flops before applying any throttling logic. This mode is particularly useful to pipeline an AXI channel pathway originating from an adjacent SLR region in a SSI device. Similar to the Fully-Registered mode, this mode supports back-to-back transfers (100% duty cycle) with one cycle of forward latency. For more on parameters and options, see the related information below.

Registered Input mode samples payload inputs and the VALID handshake input into registers, and drives registered READY handshake output as shown in the figure.

Figure 1. Registered Input AXI Register Slice Diagram

The figure shows that the registered input mode introduces one latency cycle (but no bubble cycles) in the source-to-destination payload and VALID transfer, and two cycles of latency (but no bubble cycles) in the destination-to-source READY handshake transfer.

Figure 2. Registered Input Mode Timing Diagram

When deploying two AXI Register Slice instances to cross a SLR boundary, configure each channel so that the source endpoint of the channel is fully-registered (or light-weight) and the destination endpoint has registered inputs (SI Reg or MI Reg). All signals crossing SLRs terminate at flip-flops, except the READY handshake input on each channel's source endpoint, which must directly drive handshake logic (see figure below).

Figure 3. Two AXI Register Slice Instances Diagram