Resets - 2.1 English

AXI Register Slice LogiCORE IP Product Guide (PG373)

Document ID
PG373
Release Date
2020-12-04
Version
2.1 English
Revision

The aresetn input can be tied High (inactive) if no "soft" reset is required. AXI handshake outputs remain deasserted until the device recovers from power-on reset, at which time handshake inputs are sampled. Behavioral simulation initializes to the same state as the device following power-on.

The aresetn input, if used, must be synchronized by aclk.

This IP deasserts all valid and ready outputs shortly after aresetn is sampled active, and for the duration of the aresetn pulse. AXI protocol requires that the connected master also deasserts all valid outputs during reset (until after aresetn is sampled inactive). Slaves must not assert response-channel valid outputs until after they receive a command from a master. It is also strongly recommended that slave IP deassert their ready outputs until after reset. This avoids inadvertently signaling a transfer completion in case a connected IP recovers from reset during an earlier cycle and asserts are valid.

There is no requirement that the assertion or deassertion of aresetn be observed during the same cycle or in any relative order among this IP and its connected master and slave. It is, however, required that the cycles during which reset is applied to this IP and its connected master and slave overlap. This IP does not support independent reset domains. If the master or slave device connected to this IP is reset, then all connected devices must be reset concurrently.

Recommended: As a general design guideline, Xilinx recommends asserting system aresetn signals for a minimum of 16 clock cycles, as that is known to satisfy the reset requirements.