This mode adds extra pipeline stages to optimally cross an SLR boundary in SSI devices. The SI interface of the AXI Register Slice and its connected AXI master device would then be located in one SLR, while the MI interface and its connected AXI slave device would be located in an adjacent SLR. All SLR crossings within the core are flop-to-flop with fanout = 1. This mode has been superseded by the Multi-SLR Crossing mode. See Constraining the Core section for floorplanning guidance.