SLR TDM Crossing - 2.1 English

AXI Register Slice LogiCORE IP Product Guide (PG373)

Document ID
PG373
Release Date
2020-12-04
Version
2.1 English
Revision

This adds extra pipeline stages to optimally cross one SLR boundary in SSI devices. The SI interface of the AXI Register Slice and its connected AXI master device would then be located in one SLR, while the MI interface and its connected AXI slave device would be located in an adjacent SLR. The SLR-crossing pathway consumes half the number of payload wires and propagates the cross-SLR signals at twice the frequency of the AXI interfaces. Configuring any AXI channel in this mode requires driving the aclk2x clock input with a double-frequency edge-aligned clock signal.

SLR TDM Crossing mode drives registered payload outputs and registered VALID and READY handshake outputs as shown in the figure. The submodule instance names shown can be used in cell-name patterns when writing floorplanning (Pblock) constraints, as needed, to enforce proper SLR placement.

Figure 1. SLR TDM Crossing AXI Register Slice Diagram

The figures shows that the SLR TDM Crossing mode introduces three ACLK latency cycles (but no bubble cycles) in the source-to-destination payload and VALID transfer, and one ACLK latency cycle (but no bubble cycles) in the destination-to-source READY handshake transfer.

Figure 2. SLR TDM Crossing Mode Timing Diagram