User Parameters - 2.1 English

AXI Register Slice LogiCORE IP Product Guide (PG373)

Document ID
PG373
Release Date
2020-12-04
Version
2.1 English
Revision

The following table shows the relationship between the fields in the Vivado® IDE and the user parameters (which can be viewed in the Tcl Console).

Constraining the AXI Register Slice submodules might be necessary if your implementation resulted in SLR crossings anywhere other than the intended pipelined pathway within the AXI Register Slice, typically resulting in timing-critical paths.

Table 1. User Parameters
Vivado IDE Parameter/Value 1 User Parameter/Value Default Value
REG_AW REG_AW Light
REG_W REG_W Full if PROTOCOL = AXI4 or AXI3,

Light if PROTOCOL = AXI4LIGHT

REG_B REG_B Light
REG_AR REG_AR Light
REG_R REG_R Full if PROTOCOL = AXI4 or AXI3,

Light if PROTOCOL = AXI4LIGHT

Use timing-driven pipeline insertion USE_AUTOPIPELINING 0
  1. Parameter values are listed in the table where the Vivado IDE parameter value differs from the user parameter value. Such values are shown in this table as indented below the associated parameter.

The following table shows the parameter values for the AXI Register Slice options.

Table 2. AXI Register Slice Options Parameter Values
Vivado IDE Parameter Value User Parameter Value Description
Bypass 0 Directly connects the SI to the MI
Forward 2 Only the payload and VALID handshake outputs are registered (legacy mode)
Full 1 Supports back-to-back transfers without incurring bubble cycles
Inputs 6 Only payload and handshake inputs are registered (legacy mode)
Light 7 Simple one-stage pipeline register, incurs one bubble cycle following each transfer
Multi SLR Crossing 15 Supports spanning zero or more SLR boundaries using a single instance, plus a variable number of intermediate pipeline stages per SLR
Reverse 3 Only the READY handshake output is registered (legacy mode)
SI_Reg (for REG_AW, REG_W and REG_AR), or MI_Reg (for REG_B and REG_R) 9 Passes VAILID and payload inputs on the source side through simple flip-flops, used to pipeline an AXI channel pathway originating from an adjacent SLR
SLR Crossing 10 Adds pipeline stages to optimally cross a single SLR boundary (legacy mode)
SLR TDM Crossing 11 Adds pipeline stages to optimally cross a single SLR boundary, consuming half the number of payload wires; requires 2x clock