Clock Frequency - 1.0 English

Dynamic Function eXchange Decoupler LogiCORE IP Product Guide (PG375)

Document ID

PG375

Release Date

2022-05-31

Version

1.0 English

Each clock on the core interface, whether it is a control clock, a reference clock, or a clock to be decoupled, has a parameter FREQ_HZ, which can be used to set the clock frequency. When the core is generated in out-of-context mode, these frequencies are used to set clock constraints on the core instance. The clock frequencies are managed automatically when the IP is used in the IP integrator.

Note: A clock is a signal within an interface of type xilinx.com:signal:clock_rtl. No other signal gets a FREQ_HZ parameter, even if it is named to look like a clock.

The property names are defined as:

CONFIG.<clock name>.FREQ_HZ

where <clock name> is one of the following:

aclk_CLOCK for the AXI control interface clock.
decouple_ref_clk_CLOCK for the decouple signal interface reference clock.
<interface name>_aclk_CLOCK for the interface-specific AXI clocks.
<interface name>_ref_clk_CLOCK for the interface-specific reference clocks.

Some examples are shown in the following table.

Table 1. Property Names Examples
Property Name	Description
CONFIG.aclk_CLOCK.FREQ_HZ	The AXI control interface clock.
CONFIG.intf_0_CLK_CLOCK.FREQ_HZ	A clock call CLK in an interface of type xilinx.com:signal:clock_rtl:1.0 called intf_0.

These properties can be set using the standard Vivado set_property command. Additional constraints might be required when decoupling clocks using a BUFGCE primitive or a BUFGCTRL primitive. The Vivado tools treat the data inputs to these primitives as clock, so the relationship between data input and its control input (the decouple signal) might need to be defined using constraints.