The IP integrator expects all AXI interfaces to be associated with a clock and will issue the following ciritical warning if they are not:
CRITICAL WARNING: [BD 41-968] AXI interface port <interface name> is not associated to any clock port. It may not work correctly. Please update ASSOCIATED_BUSIF parameter of a clock port to include this interface port. If this is a user packaged IP please update the IP in the IP Packager.Decoupling is combinatorial unless the register option is enabled, so clock ports are not created for AXI interfaces. A user parameter, ALWAYS_ENABLE_AXI_CLK, is available that instructs the core to enable clocks for all AXI interfaces. By default, this is disabled. AXI interface clocks are mandatory on Versal devices because of the network on chip (NoC), so the core always enables them if the family is Versal.