Clocking - 1.0 English

Dynamic Function eXchange Decoupler LogiCORE IP Product Guide (PG375)
Document ID
PG375
Release Date
2022-05-31
Version
1.0 English

The Decoupler core has several clock pins that are enabled under certain circumstances.

Table 1. Clock Pins
Name Scope Description
aclk Core Enabled when the core has an AXI control or status interface.
decouple_ref_clk Core

Enabled when aclk is disabled and one of the following conditions is true:

  1. At least one interface has clock domain crossing enabled.
  2. At least one interface is registered but has no clock domain crossing enabled.
<interface name>_aclk Interface Enabled when one of the following conditions is true:
  1. ALWAYS_HAVE_AXI_CLK is 1.
  2. The family is Versal.

If the interface does not require clock domain crossing and is not registered, then it is not used by the core. Its purpose is to help the IP integrator manage clock domains. If disabled, you might get a critical warning from the IP integrator.
<interface name>_ref_clk Interface Enabled when the interface has clock domain crossing and it does not require an AXI clock. This occurs when ALWAYS_HAVE_AXI_CLK is 0, and the family is not Versal.