The DFX Decoupler core does not normally require user constraints. However, some constraints might be required in certain circumstances, as detailed in this section.
Required Constraints
This section is not applicable for this IP core.
Device, Package, and Speed Grade Selections
The DFX Decoupler core works with any device supported by the Vivado Design Suite.
Clock Frequencies
When the core is used in an out-of-context mode, a constraints file is automatically generated to constrain all relevant clocks to the frequencies specified using the instance’s FREQ_HZ properties. You set these properties as described in Clocking.
When a signal is decoupled using a BUFGCE or a BUFGCTRL, additional constraints might be required by the tools, depending on how the instance is configured and how it is used in the system. Missing constraints will be highlighted by warning messages during implementation. For more details, see Clocking.
Clock Management
This section is not applicable for this IP core.
Clock Placement
When a signal is decoupled using a BUFGCE or a BUFGCTRL, additional constraints might be desirable to specify exactly which resources are used. For information on the instance names of these primitives, see Decoupling Using Global Routing.
Banking
This section is not applicable for this IP core.
Transceiver Placement
This section is not applicable for this IP core.
I/O Standard and Placement
This section is not applicable for this IP core.