By default, all signals selected for decoupling are decoupled using a LUT inferred by the Vivado tools. If the signal being decoupled is either a clock or a signal that needs to remain on the global routing network, the decoupler can be configured to use a BUFGCE or a BUFGCTRL primitive to implement the multiplexing.
- The BUFGCE primitive provides glitch free decoupling, but decoupling only takes effect after the input signal switches to the decoupled value. The BUFGCE primitive should only be used for clocks.
- The BUFGCTRL primitive provides instant decoupling, but it is not guaranteed to be glitch free because the IGNORE0 input is tied to 1. For more information, see the appropriate clocking guide: 7 Series FPGAs Clocking Resources User Guide (UG472), or UltraScale Architecture Clocking Resources User Guide (UG572).
If location constraints are required for these primitives, the instance name is constructed as follows:
-
b_<interface name>.<interface name>_<signal name>_<bit>_bufgce -
b_<interface name>.<interface name>_<signal name>_<bit>_bufgctrl
In the case of single bit signals, <bit> is 0.
For example, for an interface called intf_0 that contained a clock
called CLK, the name would be:
b_intf_0.intf_0_CLK_0_bufgce