Registered Interfaces - 1.0 English

Interfaces are decoupled by inserting multiplexors between the inputs and outputs, which in some cases can prevent timing closure. Each interface can be individually configured to use registers instead of multiplexors. This introduces some restrictions and, in some cases, might prevent the system from working if the VLNV being decoupled cannot handle the added latency.

AXI Memory Mapped and AXI4-Stream interfaces are registered using the AXI Memory Mapped and AXI4-Stream register slice IPs respectively, which add the following constraints to these interfaces:

1. The interface must be protocol compliant.
   1. All mandatory signals must be present with the correct widths and directions.
   2. All prohibited signals must be disabled.
2. Signals can only be decoupled to 0.
3. Only the valid and ready signals are decoupled.

For all other interfaces types, the following rules apply:

1. Registers are inserted without any consideration of the effects on the functionality of the interface protocol.
2. Signals marked as clocks in the XML that defines the VLNV will not be registered.
3. Signals configured to be implemented using buffer primitives are registered on the input to the buffer.