The UHD-SDI GT core clocking architecture depends on your selection of QPLL and its associated reference clock. The following table describes core clocks:
||100.0 MHz (Default)||All||DRPCLK frequency value valid range is device-dependent. See the respective data sheet for clock range (FGTHDRPCLK for GTH transceiver and FGTYDRPCLK for GTY transceiver)|
||148.5 MHz for integer SDI line rate or 148.35 MHz for fractional||SDI line rate GT COMMON Shared Logic is in core and QPLL0 is selected||This input clock connection depends on PLL reference clock selection|
||148.5 MHz for integer SDI line rate or 148.35 MHz for fractional||SDI line rate GT COMMON Shared Logic is in core and QPLL1 is selected||This input clock connection depends on PLL reference clock selection|
There are several clocks required in applications using GTH/GTY transceivers. The SDI protocol, which does not allow for clock correction by stuffing and removing extra data in the data stream, requires careful attention to how these clocks are generated and used in the application. GTH/GTY transceivers require reference clocks to operate. The reference clocks are used by phase-locked loops (PLLs) in the GTH/GTY transceiver quad to generate serial clocks for the receiver and transmitter sections of each transceiver. As described in GTH Transceiver Reference Clocks, the serial bit rate of the GTH/GTY transmitter is an integer multiple of the reference clock frequency it is using. Furthermore, the data rate of the video provided to the input of the SDI transmitter datapath must also exactly match (or be a specific multiple of) the frequency of the reference clock used by the GTH/GTY transmitter. Consequently, you must determine how to generate the transmitter reference clock so that it is frequency-locked exactly with the data rate of the video stream being transmitted.