GTH Transceiver Reference Clocks - 2.1 English

UHD-SDI GT LogiCORE IP Product Guide (PG380)

Document ID
2.1 English
UltraScale+™ GTH transceivers are grouped into quads. Each quad contains four GTHE4_CHANNEL transceiver primitives and one GTHE4_COMMON primitive containing two quad PLLs (QPLL0 and QPLL1) as shown in the following figure. The clock generated by the QPLL0 and QPLL1 are distributed to all four transceivers in the quad. Each GTHE4_CHANNEL has its own PLL called the Channel PLL (CPLL), which can provide a clock to the RX and TX of that transceiver only. Each RX and TX unit in the quad can be individually configured to use either/both QPLL0 or/and QPLL1 or the CPLL as its clock source. Furthermore, any RX or TX unit can dynamically switch its clock source between QPLL0, QPLL1 and CPLL. This configuration and the dynamic switching capability are particularly useful for SDI applications.
Important: The CPLL and QPLL have maximum line rates of 8.5 Gb/s and 12.5 Gb/s. This means that CPLL can only be used up to 6G-SDI line rate while QPLLs can support up to 12G-SDI for -1 speed grade UltraScale+ GTH transceivers. See GTH Transceiver Switching Characteristics section of Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922) for details when selecting the appropriate device for your application.
Figure 1. UltraScale+ GTH Transceiver Quad Configuration

Typical UHD-SDI applications require the GTH transceivers to support nine different bit rates:

  • 270 Mb/s for SD-SDI
  • 1.485 Gb/s for HD-SDI
  • 1.485/1.001 Gb/s for HD-SDI
  • 2.97 Gb/s for 3G-SDI
  • 2.97/1.001 Gb/s for 3G-SDI
  • 5.94 Gb/s for 6G-SDI
  • 5.94/1.001 Gb/s for 6G-SDI
  • 11.88 Gb/s for 12G-SDI
  • 11.88/1.001 Gb/s for 12G-SDI

The CDR unit in the RX section of the GTH/GTY transceiver can support receiving bit rates that are up to +/-1250 ppm from the reference frequency at bit rates less than 6.6 Gb/s. HD-SDI, 3G-SDI, 6G-SDI, and 12G-SDI each have two bit rates that differ by exactly 1000 ppm. For HD-SDI, 3G-SDI, and 6G-SDI, both bit rates can be received using a single reference clock frequency. That same reference clock frequency can also support reception of SD-SDI. Thus, for all SDI modes except 12G-SDI, just a single RX reference clock frequency is required. However, at 12G-SDI rates, the CDR unit has only ±200 ppm tolerance relative to the reference clock frequency. Thus two different reference clock frequencies are needed to receive the two 12G-SDI bit rates. These two reference clock frequencies are typically 148.5 MHz to receive 11.88 Gb/s and 148.5/1.001 MHz to receive 11.88/1.001 Gb/s.

Therefore, most SDI applications provide two separate reference clocks to the GTH/GTY quad. Usually, the supplied reference frequency pair are 148.5 MHz and 148.5/1.001 MHz. This documentation always refers to the reference clock frequency pair 148.5 MHz and 148.5/1.001 MHz.

The source of the GTH/GTY transceiver reference clocks is very application specific. The receiver reference clock source can be a local oscillator because it does not need to match the incoming SDI bit rate exactly. However, because the GTH/GTY transmitter line rate is always an integer multiple of the reference clock frequency, the frequency of the transmitter reference clock must be exactly related to the data rate of the transmitted data. Most often, the transmitter reference clocks are generated by genlock PLLs, thereby deriving the GTH transmitter line rate from the studio video reference signal. In some cases, such as the SDI pass-through connection, the transmitter line rate is derived from the recovered clock of the GTH receiver that is receiving the SDI signal. In such cases, an external PLL is required to reduce the jitter on the recovered clock before using it as the transmitter reference clock.

In a typical UHD-SDI application, two reference clocks are connected to QPLL0 and QPLL1. In a case where the same transceiver is used for receiving and transmitting at 12G rate, Xilinx recommends you to use CPLL-QPLL combination with CPLL for TX and QPLL0/1 for RX as shown in Figure 2. Integer and fractional rates for TX can be selected using CPLL reference clock input selection (CPLLREFCLKSEL) with 297 MHz and 296.7 MHz respectively. The RX and TX units of each transceiver in the quad dynamically switch between the PLL clocks, depending on the bit rate that is required at the moment. The GTH txsysclksel and rxsysclksel ports are used to select the TX and RX units serial clock source between the PLLs. This common configuration for SDI applications is shown in Figure 3 where multiplexers that are not used dynamically in the implementation have been replaced with wires and the reference clock routing between quads is not shown. It is also possible to the connect one reference clock to CPLL and the other to QPLL0/1.

Figure 2. Loopback Example Design GT Clocking Architecture

Also, each GTH RX and TX unit has a serial clock divider that divides the selected clock by several selectable integer powers of two. This allows, for example, all of the RX units in the quad to use the same clock frequency from the QPLL but operate at different lines rates by using different serial clock divider values. This is very useful for SD interfaces because the 3G-SDI, 6G-SDI and 12G-SDI bit rates are exactly twice as fast the HD-SDI, 3G-SDI and 6G-SDI bit rates respectively. And, for 270 Mb/s SD-SDI, the GTH transceiver runs at the 3G-SDI line rate using 11X oversampling techniques. The ability of the RX and TX units to locally divide the clock source by four divisors that differ by a factor of two is important, allowing reception and transmission of all SDI bit rates using just two reference clock frequencies.

The serial clock divider value of each RX and TX unit can be changed dynamically through the DRP, by using the RXOUT_DIV and TXOUT_DIV attributes.

The configuration shown in Figure 3 is an optimal solution for most SDI applications for several reasons:

  • The receivers can receive all SDI bit rates when using QPLL0 and QPLL1 to provide the serial clock derived from that reference clocks to all receivers in the quad.
  • The transmitters have the flexibility to dynamically switch between the clocks from QPLL0 and QPLL1 to get both frequencies they need to transmit all supported SDI bit rates.
  • When using QPLL0 and QPLL1 for 12G-SDI integer and fractional (1/1.001) rate change, switching between rates on the SDI-RX can introduce a glitch on the clock which in turn introduces CRC errors on the TX channel. CRC errors do not occur in SD-SDI/HD-SDI/ 3-G SDI/6-G SDI integer/fractional modes with QPLL0 and QPLL1 clocking combination. For more details, see Answer Record 72254 and 72449. Therefore, it is not recommended to use this clocking configuration when both transmit and receive 12G-SDI integer and fractional modes use the same transceiver. If required, Xilinx recommends to use CPLL-QPLL combination with CPLL for TX and QPLL0/1 for RX as shown in Figure 2. The integer and fractional rates for TX can be selected using CPLL reference clock input selection with 297 MHz and 296.7 MHz respectively. This CPLL/QPLL clocking combination is recommended for an UltraScale+ GTH/GTY -2 speed grade or faster rate with >0.85V because this combination is not feasible with -1 speed grade devices due to CPLL bandwidth limitation. In such a case, users must use separate GT for RX and TX to achieve a 12G-SDI line rate with -1 speed grade device. Refer the respective FPGA data sheets for CPLL line rate limits.
  • All four receivers and all four transmitters in the quad are fully independent and can each be running at different SDI bit rates and can dynamically switch between bit rates without disrupting the other RX or TX units
  • For genlocked applications, modern genlock PLLs usually can simultaneously provide both required reference clock frequencies from the synchronization reference input signal.
Figure 3. Typical GTH Reference Clock Implementation for SDI
  1. CPLL-QPLL combination with CPLL for TX and QPLL0/1 for RX GTH RX interface and internal bit width are dynamically changed through RX_DATA_WIDTH and RX_INT_DATAWIDTH DRP attributes depending on the current SDI Mode and data stream inter-leaving pattern.
  2. GTH TX interface and internal bit width are dynamically changed through TX_DATA_WIDTH and TX_INT_DATAWIDTH DRP attributes depending on the current SDI Mode and data stream inter-leaving pattern.
  3. Xilinx recommends to use a CPLL-QPLL combination with CPLL for TX and QPLL0/1 for RX where both transmit and receive at 12G-SDI integer and fractional modes are using the same transceiver as shown in Figure 2.

In some SDI applications, it might be necessary for different SDI transmitter to be running at slightly different bit rates even though they are transmitting at the same nominal bit rate. This is often the case with SDI routers where the bit rate of each TX must exactly match the bit rate of the SDI signal received by the SDI RX to which the TX is currently connected. In these cases, two transmitters that are transmitting at the same nominal bit rate, in fact, have bit rates that differ by a few ppm. Supporting such applications is possible with the UltraScale+ GTH quad architecture because each TX unit has exclusive use of its own CPLL. But to accomplish this, each CPLL must be provided with its own individual reference clock frequency, and the number of GTH/GTY reference clock inputs is limited. There are two reference clock inputs per GTH/GTY quad. A quad can use reference clocks from the quad above and the quad below. Thus, it is possible to provide some GTH quads in the device with five different reference clock frequencies (one for the RX and four for the four TX units), but overall, there are obviously not enough reference clock inputs to allow every GTH TX in the device to have its own reference clock. The PICXO technique can be very useful in these cases because it allows a GTH TX to be pulled by a few hundred ppm away from the frequency of its serial clock. Thus, applications where the bit rate of each SDI TX must be individually locked to the bit rate of the received SDI signal can be implemented by using common reference clocks as in Figure 3 and then using the PICXO technique with each GTH TX to set the exact bit rate of each SDI transmitter individually. This documentation does not cover the PICXO technique. For further information about using PICXO, contact Xilinx technical support.