Hardware Debug - 2.1 English

UHD-SDI GT LogiCORE IP Product Guide (PG380)

Document ID
PG380
Version
2.1 English

Hardware issues can range from link bring-up to problems seen after hours of testing. This section provides debug steps for common issues. The Vivado® debug feature is a valuable resource to use in hardware debug. The signal names mentioned in the following individual sections can be probed using the debug feature for debugging the specific problems.

GT Clocking
  • Make sure PLLs are getting reset before starting the IP.
  • Monitor the PLL LOCK signal. You can monitor QPLL locks using thecmp_gt_sts output port (for example, cmp_gt_sts[0] for QPLL0 Lock and cmp_gt_sts[1] for QPLL1 Lock).
  • Verify that PLL input clock frequency is of expected value.
  • It is mandatory to reset the PLL if clock input to PLL is stopped or unstable.
  • See AR 57738 for debugging GT reference clock issues.
  • Make sure to use PLL default settings from latest GT Wizard IP core based on target device.
  • Check the voltage rails on the transceivers. See AR 57737 for more information.
  • Measure RXOUTCLK is of expected frequency.
  • Make sure RXOUTCLK of the transceiver is the clock driving rx_usrclk, RXUSRCLK, and RXUSRCLK2.
  • Monitor RXBUFFSTATUS[2:0] for overflow and underflow errors.
GT Initialization
  • GTRXRESETDONE is asserted High after GT completes initialization. You can monitor GTTXRESETDONE and GTRXRESETDONE using the cmp_gt_sts output port (for example, cmp_gt_sts[5] for GTTXRESETDONE and cmp_gt_sts[8] for GTRXRESETDONE).
  • Make sure GT is not reset during normal operation.
  • See AR 59435 for more information on debugging GT reset problems.
  • Follow the recommended GT reset sequence.