RX_AXIS4S Interface Ports - 2.1 English

UHD-SDI GT LogiCORE IP Product Guide (PG380)

Document ID
PG380
Version
2.1 English
The following table describes RX_AXIS4S interface ports.
Table 1. RX_AXIS4S Interface Ports
Signal I/O Description
intf0_rxoutclk O SMPTE SDI RX core clock
intf0_rx_axis4s_ch0_tdata O

Parallel data received from transceiver. n varies with SDI standard selection: n=40 for 6G-SDI and 12G-SDI

n=20 for 3G-SDI

intf0_rx_axis4s_ch0_tvalid O Data valid
intf0_rx_axis4s_ch0_tready I SMPTE SDI RX core ready
intf0_rx_axis4s_ch0_tlast O Tuser Information. Not used.