Registering Signals - 2.1 English

UHD-SDI GT LogiCORE IP Product Guide (PG380)

Document ID
PG380
Version
2.1 English

To simplify timing and increase system performance in a programmable device design, keep all inputs and outputs registered between the user application and the core. This means that all inputs and outputs from the user application should come from, or connect to, a flip-flop. While registering signals might not be possible for all paths, it simplifies timing analysis and makes it easier for the Xilinx® tools to place and route the design.