The following features of the standard are not supported in the core:
- Standalone use; it is designed to be used with the Xilinx® UHD-SDI receiver or transmitter subsystems. See SMPTE UHD-SDI Transmitter Subsystem Product Guide (PG289) and SMPTE UHD-SDI Receiver Subsystem Product Guide (PG290) for details.
- Fractional controlled crystal oscillator (FRACXO) mode can only be supported for GTYE transceivers not for GTHE transceivers.
- Phase interpolator controlled crystal (PICXO) or FRACXO mode can only be
supported for use cases where
rx_clkoutfrequency from a GT Quad is same, hence cannot be used for RX only or TX only configurations.
- Multi-link support is available with the flexibility to choose the reference clock between QPLL0 or QPLL1, or CPLL. However, multi-link support with CPLL selection is not validated.