The Synthesizable TG supports data integrity check. Data integrity refers to the checking of the read data, against the write data that was written to the slave. To use this feature, you must first write data to a particular address. If subsequent read of the address would give the same data then data integrity will pass, else it will fail.
The Read request sent out from the AXI master is stored in a FIFO. Whenever there is a response, the request information from the FIFO is retrieved and the expected data is generated. This data is compared against the received response for validation of data integrity. If data integrity fails, the error status (along with the read request address, transaction count, and beat count) is sent to the register set that can be used for further analysis. The Synthesizable TG supports AXI Incremental, Fixed, and Wrap bursts.
A maximum of eight errors can be stored in the registers. For certain bytes, data masking during the data integrity check is supported through the register interface. The Number of Data Integrity errors to stop traffic parameter in the Vivado IDE specifies the number of errors after which the traffic must be stopped. Values supported for this parameter are 0 to 256. Setting the value to 0 never stops the traffic. The data integrity check can be disabled through the register interface.
The Synthesizable TG supports two operating modes when data integrity checking is enabled; Constant ID and Incremental ID. Each TG instance can only support one of these operating modes when set during IP configuration. While it is possible to use Incremental ID mode with fixed AXI IDs, additional considerations must be taken in to account as described in Incremental ID (Out-of-Order) Traffic.