Hardware - 1.0 English

Performance AXI Traffic Generator LogiCORE IP Product Guide (PG381)

Document ID
PG381
Release Date
2023-10-18
Version
1.0 English

After running the default traffic, the VIO interface can be used to load the block RAM with a new set of instructions to generate new traffic. The following sequence must be followed to load the block RAM and run the new traffic pattern. The addresses of the corresponding registers as well as sample addresses and data for two CSV instructions to load into the block RAM are provided.

  1. Write 0 to the SOFT_RST register (active-Low register):

    address: 0000_4000 Data: 0000_0000

  2. Write 1 to the SOFT_RST register:

    address: 0000_4000 Data: 0000_0001

  3. Load the block RAM with instructions. The addresses to load the block RAM are as follows:

    Instruction = 1;

    address = 32'h00008030; data = instruction1[12*32+:32]

    address = 32'h0000802c; data = instruction1[11*32+:32]

    address = 32'h00008028; data = instruction1[10*32+:32]

    address = 32'h00008024; data = instruction1[9*32+:32]

    address = 32'h00008020; data = instruction1[8*32+:32]

    address = 32'h0000801c; data = instruction1[7*32+:32]

    address = 32'h00008018; data = instruction1[6*32+:32]

    address = 32'h00008014; data = instruction1[5*32+:32]

    address = 32'h00008010; data = instruction1[4*32+:32]

    address = 32'h0000800c; data = instruction1[3*32+:32]

    address = 32'h00008008; data = instruction1[2*32+:32]

    address = 32'h00008004; data = instruction1[1*32+:32]

    address = 32'h00008000; data = instruction1[0*32+:32]

    Instruction =2

    address = 32'h00008070; data = instruction2[12*32+:32]

    address = 32'h0000806c; data = instruction2[11*32+:32]

    address = 32'h00008068; data = instruction2[10*32+:32]

    address = 32'h00008064; data = instruction2[9*32+:32]

    address = 32'h00008060; data = instruction2[8*32+:32]

    address = 32'h0000805c; data= instruction2[7*32+:32]

    address = 32'h00008058; data = instruction2[6*32+:32]

    address = 32'h00008054; data = instruction2[5*32+:32]

    address = 32'h00008050; data = instruction2[4*32+:32]

    address = 32'h0000804c; data = instruction2[3*32+:32]

    address = 32'h00008048; data = instruction2[2*32+:32]

    address = 32'h00008044; data = instruction2[1*32+:32]

    address = 32'h00008040; data = instruction2[0*32+:32]

  4. Write 1 to the TG_START register to start the traffic:

    Address: 00004004; Data: 0000_0001

Refer to Address Decoding for Synthesizable TG for more information on these registers