Parity Generation - 1.0 English

Performance AXI Traffic Generator LogiCORE IP Product Guide (PG381)

Document ID
PG381
Release Date
2023-10-18
Version
1.0 English
Performance AXI Traffic Generator IP has the capability to compute even parity for both AXI addresses and data and send this parity information as part of AXUSER and WUSER signals. In the Configuration tab of TG GUI , the Enable Parity option is used for enabling or disabling the parity generator. On enabling this option, you see two additional options in the GUI, Number of Data Bits per Parity Bit and Number of Address bits per Parity Bit as shown in the following picture.
Figure 1. Parity Generation

For example, if AXI Address Width = 48 and Number of Address bits per parity bit = 8, then,

Number of Address parity bits = AXI Address Width / Number of Address bits per parity bit = 6 bits.

These bits are appended with awuser and aruser bits as per the following table.

If AXI Data Width = 512 and Number of Data bits per parity bit = 8, then,

Number of Data parity bits = AXI Data Width / Number of Data bits per parity bit = 64 bits

These will be appended to the wuser bits as per the following table. The parity is only generated from the TG and there is no parity check for the read channel.

Note: The parameters Number of Data Bits per Parity Bit and Number of Address Bits per Parity Bit is not user programmable. Its value is programmed based on the AXI user width field.
Table 1. AXI Address and Data Parity
AXI Bus Enabled Disabled
AWUSER

18

2 bits reserved (0s)

6 bits parity

10 bits user data

16

6 bits reserved (0s)

10 bits user data

ARUSER

18

2 bits reserved (0s)

6 bits parity

10 bits user data

16

6 bits reserved (0s)

10 bits user data

WUSER

2*(AXI_DATA_BUS_WIDTH/8)

Parity bits in odd bit positions. Poison bits in even positions.

16

16 bits reserved (0s)