| Bit | Default Value | Access Type | Description |
|---|---|---|---|
| 31:1 | 0 | R/W | Reserved |
| 0 | 0 | R/W | When set, enables the TG to send the traffic. It is a self-clearing register. |
| Bit | Default Value | Access Type | Description |
|---|---|---|---|
| 31:1 | 0 | R/W | Reserved |
| 0 | 0 | R/W | When set, enables the TG to send the traffic. It is a self-clearing register. |