The Traffic Generator operation for AXI4 configuration is shown in the following figure.
The TG is designed to support high bandwidth bidirectional data transfers. An instruction block RAM is present in the instruction core module of the TG with a depth of 512. This means up to 512 CSV instructions can be loaded in the block RAM and each CSV instruction can have up to 65,536 Write/Read requests or a single Wait request.
When the instruction block RAM is loaded with any of the supported Modes of Operation and the TG start signal is asserted, the instruction core module reads the instruction from the block RAM and writes in the Write or Read Channel FIFO based on that instruction.
The Write Instruction Fetch module reads the data from Write Channel FIFO and gives it to the Write Channel Control module. Based on the information in the instruction fields, the AXI Write command and Write data are generated based on the data pattern selection. The second Write request is sent only after sending the data from the first Write request.
The Read Instruction Fetch module reads the data from the Read Channel FIFO and gives it to the Read Channel Control module. Based on the information in the instruction fields, the AXI Read command is generated. The Read requests are issued back to back without any Wait cycles.
Latency and data integrity modules are optional and you can enable them during IP generation. The data integrity module, if enabled, checks for the response data and reports errors to the register space when a data mismatch occurs. The TG also supports infinite transaction and infinite loop counts that allows the TG to run indefinitely.