The Traffic Generator reads and executes instructions in the block RAM. CSV instructions can be loaded in the block RAM on the fly using VIO or the AXI4-Lite interface and can run unlimited test cases on the board using a single bit file. When a CSV file is specified in the Vivado IDE, the block RAM is already populated with the instruction information.
The TG has a register space with a set of configurations and status registers. Configuration registers such as soft reset or TG start are present in the register space and can be modified through VIO or AXI4-Lite interfaces.
TG status information is also stored in the status registers. You can read registers such as the bandwidth counters, transaction counters and error registers through the VIO or AXI4-Lite interfaces.