The instruction block RAM must be loaded with instructions to run the traffic. These instructions can be loaded on the fly using virtual input/output (VIO). VIO is instantiated in the Simulation Trigger module. A Tcl script is used to load the instruction block RAM through VIO. The script takes the MEM file as input and generates Tcl commands that VIO can understand. Run this Tcl script in the Tcl console in the Vivado Hardware Manager to load the instruction block RAM or to read/write from the register space. A block diagram of the VIO interface is shown in the following figure.
Figure 1. VIO Interface Block Diagram
The VIO interface signals in the Simulation Trigger module are shown in the following table.
| Signal Name | Direction | Width | Description |
|---|---|---|---|
vio_wren
|
O | 1 | Write Enable. If vio_wren is High it writes into the
config register. |
vio_rden
|
O | 1 | Read Enable. If vio_rden is High it reads from the
config/status register. |
vio_addr_t
|
O | 32 | Register address. |
vio_wdata
|
O | 32 | Write data. |
vio_rdvalid
|
I | 1 | Read Valid. If vio_rdvalid is High the
vio_rdata is valid. |
vio_rdata
|
I | 32 | Valid Read data. |