Core Specifics |
Supported Device Family
1
|
Versal™
ACAPs,
UltraScale+™
devices,
UltraScale™
devices,
Zynq®
UltraScale+™ MPSoCs,
Zynq®-7000 SoCs, 7 series FPGAs |
Supported User Interfaces |
CDC Interface |
Provided with Core
|
Design Files |
System Verilog |
Example Design |
N/A |
Test Bench |
N/A |
Constraints File |
N/A |
Simulation Model |
N/A |
Supported S/W Driver |
N/A |
Tested Design Flows |
Design Entry |
IP Integrator |
Simulation |
For supported simulators, see Xilinx Design Tools: Release Notes
Guide. |
Synthesis |
Vivado Synthesis |
Support |
All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
Xilinx Support web page. |
- For a complete list of supported devices, see
the
Vivado®
IP catalog.
- For the supported versions of third-party
tools, see the Xilinx Design Tools: Release Notes Guide.
|