The following table describes XPM CDC Generator core ports.
Port | I/O | Width | Domain | Sense | Handling if Unused | Function |
---|---|---|---|---|---|---|
dest_clk | I | 1 | N/A | EDGE_RISING | Active | The clock signal for the destination clock domain. |
dest_out | O | WIDTH | dest_clk | N/A | Active | src_in synchronized to the destination clock domain. This output is registered. |
src_clk | I | 1 | N/A | EDGE_RISING | 0 | Unused when SRC_INPUT_REG = 0. Input clock signal for src_in if SRC_INPUT_REG = 1. |
src_in | I | WIDTH | src_clk | N/A | Active |
Input single-bit array to be synchronized to the destination clock domain. It is assumed that each bit of the array is unrelated to the others. This is reflected in the constraints applied to this macro. To transfer a binary value losslessly across the two clock domains, use the XPM_CDC_GRAY macro instead. |
dest_arst | O | 1 | dest_clk | N/A | Active | src_arst asynchronous reset signal synchronized to destination
clock domain. This output is registered. Note: Signal asserts asynchronously but deasserts
synchronously to dest_clk. The width of the reset signal is at least
(DEST_SYNC_FF*dest_clk) period.
|
src_arst | I | 1 | N/A | N/A | Active | Source asynchronous reset signal. |
dest_out_bin | O | WIDTH | dest_clk | N/A | Active | Binary input bus (src_in_bin) synchronized to destination clock domain. This output is combinatorial unless REG_OUTPUT is set to 1. |
src_in_bin | I | WIDTH | src_clk | N/A | Active | Binary input bus that is synchronized to the destination clock domain. |
dest_req | O | 1 | dest_clk | LEVEL_HIGH | Active | This assertion of this signal indicates that new dest_out data
has been received and is ready to be used or captured by the destination logic.
This output is registered. |
src_rcv | O | 1 | src_clk | LEVEL_HIGH | Active |
Acknowledgment from destination logic that src_in has been received. This signal is deasserted when the destination handshake has fully completed, thus completing a full data transfer. This output is registered. |
src_send | I | 1 | src_clk | LEVEL_HIGH | Active | The assertion of this signal allows the src_in bus to be
synchronized to the destination clock domain.
|
dest_pulse | O | 1 | dest_clk | LEVEL_HIGH | Active | Outputs a pulse that is the size of one dest_clk period when a pulse transfer is correctly initiated on src_pulse input. This output is combinatorial unless REG_OUTPUT is set to 1. |
dest_rst_in | I | 1 | dest_clk | LEVEL_HIGH | 0 |
Unused when RST_USED = 0. Destination reset signal if RST_USED = 1. Resets all logic in the destination clock domain. To fully reset the macro, src_rst and dest_rst must be asserted simultaneously for at least ((DEST_SYNC_FF + 2) * dest_clk_period) + (2 * src_clk_period). |
src_pulse | I | 1 | src_clk | EDGE_RISING | Active |
The rising edge of this signal initiates a pulse transfer to the destination clock domain. The minimum gap between each pulse transfer must be at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured between the falling edge of a src_pulse to the rising edge of the next src_pulse. This minimum gap guarantees that each rising edge of src_pulse will generate a pulse the size of one dest_clk period in the destination clock domain. When RST_USED = 1, pulse transfers are not guaranteed while src_rst and/or dest_rst are asserted. |
src_rst | I | 1 | src_clk | LEVEL_HIGH | 0 |
Unused when RST_USED = 0. Source reset signal if RST_USED = 1. Resets all logic in the source clock domain. To fully reset the macro, src_rst and dest_rst must be asserted simultaneously for at least ((DEST_SYNC_FF + 2) * dest_clk_period) + (2 * src_clk_period). |
dest_rst_out | O | 1 | dest_clk | N/A | Active | This is src_rst synchronized to the destination clock domain. This output is registered. |