User Parameters - 1.0 English

The following table shows the relationship between the fields in the Vivado® IDE and the user parameters (which can be viewed in the Tcl Console).

Table 1. User Parameters
Attribute	Type	Allowed Values	Default	Description
DEST_SYNC_FF	DECIMAL	2 to 10	4	The number of register stages used to synchronize signal in the destination clock domain.
INIT_SYNC_FF	DECIMAL	0, 1	0	Disable behavioral simulation initialization value(s) on synchronization registers. Enable behavioral simulation initialization value(s) on synchronization registers.
SIM_ASSERT_CHK	DECIMAL	0, 1	0	Disable simulation message reporting. Messages related to potential misuse will not be reported. Enable simulation message reporting. Messages related to potential misuse will be reported.
SRC_INPUT_REG	DECIMAL	1, 0	1	Do not register input (`src_in`) Register input (`src_in`) once using `src_clk`
WIDTH	DECIMAL	1 to 1024	2	Width of the single-bit array (src_in) that will be synchronized to the destination clock domain.
REG_OUTPUT	DECIMAL	0, 1	0	0: Disable registered output 1: Enable registered output
SIM_ASSERT_CHK	DECIMAL	0, 1	0	Disable simulation message reporting. Messages related to potential misuse will not be reported. Enable simulation message reporting. Messages related to potential misuse will be reported.
SIM_LOSSLESS_GRAY_CHK	DECIMAL	0, 1	0	Disable simulation message that reports whether src_in_bin is incrementing or decrementing by one, guaranteeing lossless synchronization of a gray coded bus. Enable simulation message that reports whether src_in_bin is incrementing or decrementing by one, guaranteeing lossless synchronization of a gray coded bus.
DEST_EXT_HSK	DECIMAL	1, 0	0	An internal handshake will be implemented in the macro to acknowledge receipt of data on the destination clock domain. When using this option, the valid dest_out output must be consumed immediately to avoid any data loss. The user must implement external handshake logic to acknowledge receipt of data on the destination clock domain.
REG_OUTPUT	DECIMAL	0, 1	0	0: Disable registered output. 1: Enable registered output.
RST_USED	DECIMAL	1, 0	1	0: No resets implemented. 1: Resets implemented. When RST_USED = 0, `src_pulse` input must always be defined during simulation because there is no reset logic to recover from an x-propagating through the macro.
REG_OUTPUT	DECIMAL	0, 1	0	0: Disable registered output 1: Enable registered output
RST_USED	DECIMAL	1, 0	1	0: No resets implemented. 1: Resets implemented. When RST_USED = 0, `src_pulse` input must always be defined during simulation because there is no reset logic to recover from an x-propagating through the macro.
WIDTH	DECIMAL	1 to 1024	1	Width of the bus that is synchronized to the destination clock domain.
INIT	DECIMAL	1, 0	1	Initializes synchronization registers to 0 Initializes synchronization registers to 1 The option to initialize the synchronization registers means that no complete x- propagation behavior is modeled in this macro. For complete x-propagation modeling, use the xpm_cdc_single macro.