- MACRO_GROUP: XPM
- MACRO_SUBGROUP: XPM_CDC
Introduction
This macro synthesizes an array of single-bit signals from the source clock domain to the destination clock domain.
For proper operation, the input data must be sampled two or more times by the destination clock. You can define the number of register stages used in the synchronizers. An optional input register can be used to register the input in the source clock domain prior to it being synchronized. You can also enable a simulation feature to generate messages to report any potential misuse of the macro.
Port Descriptions
Port | I/O | Width | Domain | Sense | Handling if Unused | Function |
---|---|---|---|---|---|---|
dest_clk | I | 1 | N/A | EDGE _RISING | Active | Clock signal for the destination clock domain. |
dest_out | O | WIDTH | dest_clk | N/A | Active | This is src_in synchronized to the destination clock domain. This output is registered. |
src_clk | I | 1 | N/A | EDGE _RISING | 0 | Unused when SRC_INPUT_REG = 0. Input clock signal for src_in if SRC_INPUT_REG = 1. |
src_in | I | WIDTH | src_clk | N/A | Active |
Input single-bit array to be synchronized to destination clock domain. It is assumed that each bit of the array is unrelated to the others. This is reflected in the constraints applied to this macro. To transfer a binary value losslessly across the two clock domains, use the XPM_CDC_GRAY macro instead. |
Design Entry Method
Design Entry | Yes/No |
---|---|
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | Yes |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
DEST_SYNC_FF | DECIMAL | 2 to 10 | 4 | Number of register stages used to synchronize signal in the destination clock domain. |
INIT_SYNC_FF | DECIMAL | 0, 1 | 0 |
|
SIM_ASSERT_CHK | DECIMAL | 0, 1 | 0 |
|
SRC_INPUT_REG | DECIMAL | 1, 0 | 1 |
|
WIDTH | DECIMAL | 1 to 1024 | 2 | Width of single-bit array (src_in) that will be synchronized to destination clock domain. |