XPM_CDC_ASYNC_RST - 1.0 English

XPM CDC Generator v1.0 LogiCORE IP Product Guide (PG382)

Document ID
PG382
Release Date
2021-02-09
Version
1.0 English
  • MACRO_GROUP: XPM
  • MACRO_SUBGROUP: XPM_CDC

Introduction

This macro synchronizes an asynchronous reset signal to the destination clock domain. The resulting reset output is guaranteed to assert asynchronously in relation to the input but the deassertion of the output will always be synchronous to the destination clock domain.

You can define the polarity of the reset signal and the minimal output pulse width of the macro when asserted. The latter is controlled by defining the number of register stages used in the synchronizers.

Note: The minimum input pulse assertion is dependent on the setup and hold requirement of the reset or set pin of the registers. See the respective DC and AC switching characteristics data sheets for the targeted architecture.

Port Descriptions

Table 1. Port Descriptions
Port I/O Width Domain Sense Handling if Unused Function
dest_arst O 1 dest_clk N/A Active

This is the src_arst asynchronous reset signal synchronized to the destination clock domain. This output is registered.

Note: Signal asserts asynchronously but deasserts synchronously to dest_clk. Width of the reset signal is at least (DEST_SYNC_FF*dest_clk) period.
dest_clk I 1 N/A EDGE _RISING Active Destination clock.
src_arst I 1 N/A N/A Active Source asynchronous reset signal.

Design Entry Method

Table 2. Design Entry Method
Design Entry Yes/No
Instantiation Yes
Inference No
IP and IP Integrator Catalog Yes

Available Attributes

Table 3. Available Attributes
Attribute Type Allowed Values Default Description
DEST_SYNC_FF DECIMAL 2 to 10 4 Number of register stages used to synchronize signal in the destination clock domain. This parameter also determines the minimum width of the asserted reset signal.
INIT_SYNC_FF DECIMAL 0, 1 0
  • 0: Disable behavioral simulation initialization value(s) on synchronization registers.
  • 1: Enable behavioral simulation initialization value(s) on synchronization registers.
RST_ACTIVE_HIGH DECIMAL 0, 1 0

Defines the polarity of the asynchronous reset signal.

  • 0: active-Low asynchronous reset signal
  • 1: active-High asynchronous reset signal