XPM_CDC_GRAY - 1.0 English

MACRO_GROUP: XPM
MACRO_SUBGROUP: XPM_CDC

Introduction

This macro synchronizes a binary input from the source clock domain to the destination clock domain using gray code. For proper operation, the input data must be sampled two or more times by the destination clock.

This module takes the input binary signal, translates it into Gray code and registers it, synchronizes it to the destination clock domain, and then translates it back to a binary signal. You can define the number of register stages used in the synchronizers. You can also enable a simulation feature to generate messages to report any potential misuse of the macro.

Because this macro uses Gray encoding, the binary value provided to the macro must only increment or decrement by one to ensure that the signal being synchronized has two successive values that only differ by one bit. This ensures lossless synchronization of a Gray coded bus. If the behavior of the binary value is not compatible with Gray encoding, use the XPM_CDC_HANDSHAKE macro or an alternate method of synchronizing the data to the destination clock domain.

An additional option (SIM_LOSSLESS_GRAY_CHK) is provided to report an error message when any binary input values are found to violate the Gray coding rule where two successive values must only increment or decrement by one.

Note: When the XPM_CDC_GRAY module is used in a design and report_cdc is run, the synchronizer in this module is reported as a warning of type CDC-6, Multi-bit synchronized with ASYNC_REG property. This warning is safe to ignore because the bus that is synchronized is gray-coded. Starting in 2018.3, this warning has been suppressed by adding a CDC-6 waiver to the Tcl constraint file.

You should run report_cdc to make sure the CDC structure is identified and that no critical warnings are generated, and also verify that dest_clk can sample src_in_bin[n:0] two or more times.

Port Descriptions

Table 1. Port Descriptions
Port	I/O	Width	Domain	Sense	Handling if Unused	Function
dest_clk	I	1	N/A	EDGE _RISING	Active	Destination clock.
dest_out_bin	O	WIDTH	dest_clk	N/A	Active	Binary input bus (src_in_bin) synchronized to destination clock domain. This output is combinatorial unless REG_OUTPUT is set to 1.
src_clk	I	1	N/A	EDGE _RISING	Active	Source clock.
src_in_bin	I	WIDTH	src_clk	N/A	Active	Binary input bus that will be synchronized to the destination clock domain.

Design Entry Method

Table 2. Design Entry Method
Design Entry	Yes/No
Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	Yes

Available Attributes

Table 3. Available Attributes
Attribute	Type	Allowed Values	Default	Description
DEST_SYNC_FF	DECIMAL	2 to 10	4	Number of register stages used to synchronize signal in the destination clock domain.
INIT_SYNC_FF	DECIMAL	0, 1	0	0: Disable behavioral simulation initialization value(s) on synchronization registers. 1: Enable behavioral simulation initialization value(s) on synchronization registers.
REG_OUTPUT	DECIMAL	0, 1	0	0: Disable registered output 1: Enable registered output
SIM_ASSERT_CHK	DECIMAL	0, 1	0	0: Disable simulation message reporting. Messages related to potential misuse will not be reported. 1: Enable simulation message reporting. Messages related to potential misuse will be reported.
SIM_LOSSLESS _GRAY_CHK	DECIMAL	0, 1	0	0: Disable simulation message that reports whether src_in_bin is incrementing or decrementing by one, guaranteeing lossless synchronization of a gray coded bus. 1: Enable simulation message that reports whether src_in_bin is incrementing or decrementing by one, guaranteeing lossless synchronization of a gray coded bus.
WIDTH	DECIMAL	2 to 32	2	Width of binary input bus that will be synchronized to destination clock domain.