- MACRO_GROUP: XPM
- MACRO_SUBGROUP: XPM_CDC
Introduction
This macro uses a handshake signaling to transfer an input bus from the source clock domain to the destination clock domain. One example of when this macro should be used is when the data being transferred is not compatible with the XPM_CDC_GRAY macro that uses Gray encoding.
For this macro to function correctly, a full handshake—an acknowledgment that the data transfer was received and a resetting of the handshake signals—must be completed before another data transfer is initiated.
You can define the number of register stages used in the synchronizers to
transfer the handshake signals between the clock domains individually. You can also
include internal handshake logic to acknowledge the receipt of data on the
destination clock domain. When this feature is enabled, the output
(dest_out
) must be consumed immediately when the data valid
(dest_req
) is asserted.
report_cdc
is run, the data bus that is synchronized in this
module is reported as a warning of type CDC-15, Clock Enable Controlled CDC.
This warning is safe to ignore. Starting in 2018.3, this warning has been
suppressed by adding a CDC-15 waiver to the Tcl constraint file.You should run report_cdc
to make sure the CDC structure is
identified and that no critical warnings are generated, and also verify that
dest_clk
can sample src_in
[n:0] two or more
times.
External Handshake
The following waveform shows how back-to-back data is sent when the external handshake option is used.
Internal Handshake
The following waveform shows how back-to-back data is sent when the internal handshake option is enabled.
Port Descriptions
Port | I/O | Width | Domain | Sense | Handling if Unused | Function |
---|---|---|---|---|---|---|
dest_ack | I | 1 | dest_clk | LEVEL _HIGH | 0 |
Destination logic acknowledgement if DEST_EXT_HSK = 1. Unused when DEST_EXT_HSK = 0. Asserting this signal indicates that data on dest_out has been captured by the destination logic. This signal should be deasserted once dest_req is deasserted, completing the handshake on the destination clock domain and indicating that the destination logic is ready for a new data transfer. |
dest_clk | I | 1 | N/A | EDGE _RISING | Active | Destination clock. |
dest_out | O | WIDTH | dest_clk | N/A | Active | Input bus (src_in) synchronized to destination clock domain. This output is registered. |
dest_req | O | 1 | dest_clk | LEVEL _HIGH | Active |
Assertion of this signal indicates that new dest_out data has been received and is ready to be used or captured by the destination logic.
This output is registered. |
src_clk | I | 1 | N/A | EDGE _RISING | Active | Source clock. |
src_in | I | WIDTH | src_clk | N/A | Active | Input bus that will be synchronized to the destination clock domain. |
src_rcv | O | 1 | src_clk | LEVEL _HIGH | Active |
Acknowledgement from destination logic that src_in has been received. This signal will be deasserted once destination handshake has fully completed, thus completing a full data transfer. This output is registered. |
src_send | I | 1 | src_clk | LEVEL _HIGH | Active | Assertion of this signal allows the src_in bus to be synchronized to
the destination clock domain.
|
Design Entry Method
Design Entry | Yes/No |
---|---|
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | Yes |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
DEST_EXT_HSK | DECIMAL | 1, 0 | 1 |
|
DEST_SYNC_FF | DECIMAL | 2 to 10 | 4 | Number of register stages used to synchronize signal in the destination clock domain. |
INIT_SYNC_FF | DECIMAL | 0, 1 | 0 |
|
SIM_ASSERT_CHK | DECIMAL | 0, 1 | 0 |
|
SRC_SYNC_FF | DECIMAL | 2 to 10 | 4 | Number of register stages used to synchronize signal in the source clock domain. |
WIDTH | DECIMAL | 1 to 1024 | 1 | Width of bus that will be synchronized to destination clock domain. |