XPM_CDC_SINGLE - 1.0 English

MACRO_GROUP: XPM
MACRO_SUBGROUP: XPM_CDC

Introduction

This macro synchronizes a one bit signal from the source clock domain to the destination clock domain.

For proper operation, the input data must be sampled two or more times by the destination clock. You can define the number of register stages used in the synchronizers. An optional input register may be used to register the input in the source clock domain prior to it being synchronized. You can also enable a simulation feature to generate messages to report any potential misuse of the macro.

Port Descriptions

Table 1. Port Descriptions
Port	I/O	Width	Domain	Sense	Handling if Unused	Function
dest_clk	I	1	N/A	EDGE _RISING	Active	Clock signal for the destination clock domain.
dest_out	O	1	dest_clk	N/A	Active	This is src_in synchronized to the destination clock domain. This output is registered.
src_clk	I	1	N/A	EDGE _RISING	0	Input clock signal for src_in if SRC_INPUT_REG = 1. Unused when SRC_INPUT_REG = 0.
src_in	I	1	src_clk	N/A	Active	Input signal to be synchronized to dest_clk domain.

Design Entry Method

Table 2. Design Entry Method
Design Entry	Yes/No
Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	Yes

Available Attributes

Table 3. Available Attributes
Attribute	Type	Allowed Values	Default	Description
DEST_SYNC_FF	DECIMAL	2 to 10	4	Number of register stages used to synchronize signal in the destination clock domain.
INIT_SYNC_FF	DECIMAL	0, 1	0	0: Disable behavioral simulation initialization value(s) on synchronization registers. 1: Enable behavioral simulation initialization value(s) on synchronization registers.
SIM_ASSERT_CHK	DECIMAL	0, 1	0	0: Disable simulation message reporting. Messages related to potential misuse will not be reported. 1: Enable simulation message reporting. Messages related to potential misuse will be reported.
SRC_INPUT_REG	DECIMAL	1, 0	1	0: Do not register input (`src_in`) 1: Register input (`src_in`) once using `src_clk`