- MACRO_GROUP: XPM
- MACRO_SUBGROUP: XPM_CDC
Introduction
This macro synchronizes a reset signal to the destination clock domain. Unlike the XPM_CDC_ASYNC_RST macro, the generated output will both assert and deassert synchronously to the destination clock domain.
For proper operation, the input data must be sampled two or more times by the destination clock. You can define the number of register stages used in the synchronizers and the initial value of these registers after configuration. You can also enable a simulation feature to generate messages which report any potential misuse of the macro.
Port Descriptions
Port | I/O | Width | Domain | Sense | Handling if Unused | Function |
---|---|---|---|---|---|---|
dest_clk | I | 1 | N/A | EDGE _RISING | Active | Destination clock. |
dest_rst_out | O | 1 | dest_clk | N/A | Active | This is src_rst synchronized to the destination clock domain. This output is registered. |
src_rst | I | 1 | N/A | N/A | Active | Source reset signal. |
Design Entry Method
Design Entry | Yes/No |
---|---|
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | Yes |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
DEST_SYNC_FF | DECIMAL | 2 to 10 | 4 | Number of register stages used to synchronize signal in the destination clock domain. |
INIT | DECIMAL | 1, 0 | 1 |
The option to initialize the synchronization registers means that there is no complete x-propagation behavior modeled in this macro. For complete x-propagation modeling, use the xpm_cdc_single macro. |
INIT_SYNC_FF | DECIMAL | 0, 1 | 0 |
|
SIM_ASSERT_CHK | DECIMAL | 0, 1 | 0 |
|