Data center storage is evolving at a rapid pace due to the emergence of newer storage technologies such as NVMe and 3D-XPoint coupled with the introduction of SmartNICs that can offload some of the critical processing to the network interface controller while being programmable. This puts a demand on system components to support line-rate processing of data. Encryption is at the heart of any such application and the Xilinx® AES IP has been designed to meet the demand for high performance encryption cores that can be seamlessly integrated into these systems.
These cores can also be used for applications ranging from communication systems to advanced driver-assistance systems (ADAS) and self-driving cars. The core also supports a lightweight, low resource count variant for applications such as smart card readers that do not need to perform at high-speeds. The core provides industry-leading performance enabled by several patent-pending architectural innovations.
The major components of the core are the AES encryption/decryption engines, the metadata generation block, key expansion, and control logic. The AES engines are swapped between their high and low-throughput variants based on the option you selected.
The core supports the following AES variants:
- AES-XTS-256 (without CTS)
- AES-XTS-128 (without CTS)