This chapter provides information about the example design, including a description of the files and the directory structure generated by the Xilinx® Vivado® Design Suite, the purpose and contents of the provided scripts, the contents of the example HDL wrappers, and the operation of the demonstration test bench.
The following figure shows a snapshot of the example design for a core generated with the default configuration.
The example design has a self-checking setup in which random AXI4-Stream traffic is generated by the AXI Traffic Generator IP, and sent to the DUT to encrypt/decrypt the data. The output of the DUT is sent to a DUT partner which is configured as the opposite type of the DUT. This means that a DUT generated for encryption would be paired with a partner that would run decryption and vice versa, keeping all the other parameters the same. The output of the partner is sent back to the AXI Traffic Generator to compare with the original data. A test bench is provided to run the example design and then print the result of the comparison.
The example design also instantiate block RAMs through the block Memory
Generator IP for key and IV for all the blocks in the data for both the DUT and the partner.
It also includes the
mem_addr_gen_v1_0 module that uses the
key_fetch indication from the IP to increment the block RAM
address and fetch the next set of metadata from the respective block RAMs. The
key_valid input to the core is tied to logic "1" because all the
keys and IV are readily available in the block RAM. This subsystem design is inspired from a
typical storage encryption solution commonly used in the data centers.