Clocking - 2.1 English

Lossless Compression LogiCORE IP Product Guide (PG387)

Document ID
PG387
Release Date
2022-11-18
Version
2.1 English
Compression Mode
In this mode, the core runs with three clocks:
  • s_aclk_250
  • s_aclk_500
  • clk_hf
The s_aclk_500 is twice the frequency of s_aclk_250. Both s_aclk_250 and the s_aclk_500 clocks should be phase-aligned and originate from same clock source. The clk_hf clock is asynchronous to the s_aclk_250 and s_aclk_500 clocks. Meeting the same frequency when the core is inserted into a system is subject to the system design, device congestion, usage of timing best practices, and other factors.
Decompression Mode
In this mode, the core runs on a single clock through the port named s_aclk. The core is tested to meet timing at 250 MHz when measured at the IP level. Meeting the same frequency when the core is inserted into a system is subject to the system design, device congestion, and the usage of timing best practices, and other factors.