|
Core Specifics |
| Supported Device Family
1, 3
|
Versal®
ACAP,
UltraScale+™
and
UltraScale™
Devices |
| Supported User Interfaces |
AXI4-Stream
|
| Resources |
Resource Utilization web page
|
| Provided with Core
|
| Design Files |
Encrypted RTL |
| Example Design |
Verilog |
| Test Bench |
Not Provided |
| Constraints File |
Xilinx Constraints File (XDC) |
| Simulation Model |
Not Provided |
| Supported S/W Driver
|
N/A |
| Tested Design
Flows
2
|
| Design Entry |
Vivado® Design Suite
|
| Simulation |
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide. |
| Synthesis |
Vivado
Synthesis |
| Support |
| All Vivado IP Change Logs |
Master Vivado
IP Change Logs: 72775
|
|
Xilinx
Support web page
|
- For a complete list of supported devices, see the
Vivado®
IP catalog.
- For the supported versions of third-party
tools, see the Xilinx Design Tools: Release Notes
Guide.
- UltraScale devices are not supported for
compression mode.
|