Interface Ports - 2.1 English

Lossless Compression LogiCORE IP Product Guide (PG387)
Document ID
PG387
Release Date
2022-11-18
Version
2.1 English
Table 1. Lossless Compression IP Ports
Port Name I/O Description
s_aclk I Clock signal for the core in the Decompression mode.
s_aclk_250 I Clock signal for the core in the Compression mode.
s_aclk_500 I Clock signal for the core in the Compression mode.
clk_hf I Clock signal used for huffman in the compression mode
s_aresetn I Active-Low reset signal for the core.
s_axis_tdata[dw-1:0] I Input AXI4-Stream data. dw is Input Data Width. dw is fixed to 256 in compression mode.
s_axis_tkeep[dw/8-1:0] I

Input AXI4-Stream signal. Indicates the bytes in the data that are valid. dw is Input Data Width. dw is fixed to 256 in compression mode.
s_axis_tvalid I Input AXI4-Stream data valid signal.
s_axis_tlast I

Input AXI4-Stream signal. Indicates the last beat of the input file being compressed/decompressed.
s_axis_tready O

Output AXI4-Stream signal. Indicates that the core is ready to consume another beat of data.
m_axis_tdata[255:0] O Output AXI4-Stream data.
m_axis_tkeep[31:0] O

Output AXI4-Stream signal. Indicates the bytes in the data that are valid.
m_axis_tvalid O Output AXI4-Stream data valid signal.
m_axis_tlast O

Output AXI4-Stream signal. Indicates the last beat of the output file after being compressed/decompressed.
m_axis_tready I

Output AXI4-Stream signal. Indicates the last beat of the output file after being compressed/decompressed.

m_axis_tuser[35:0] O
This is a 36-bit port indicating the compressed/decompressed file size and info about some errors detected.
  • Compression Mode: Bits 31:0 represents the compressed file size. Bits 35:32 - Reserved.
  • Decompression Mode:
    • Bits 31:0 represents the decompressed file size.
    • Bit 32 - There can be errors in any part of the file header.

    • Bit 33 - This bit will go high whenever the starting part of the header has neither GZIP nor ZLIB format.

    • Bit 34 - Error in compressed input data.
    • Bit 35 - Checksum error
Note: The s_aclk_500 clock is twice the frequency of s_aclk_250 clock. Both s_aclk_250 and the s_aclk_500 clocks should be phase-aligned and originate from same clock source.
Note: err_info ports present in v1.0 version of the IP are moved to m_axis_tuser port of this version of the IP. Please refer to Table 1.
Note: All the AXI-Stream ports mentioned in the previous table are operated with s_aclk_250 for Compression mode. In Decompression mode, they are operated with s_aclk.
Important: If the IP gives out an error signal (m_axis_tuser[35:32]), the IP needs to be given a reset signal of minimum 1 clock pulse for it to function properly.