For stable data sampling, data transition should occur in the centre of the clock. This can be controlled using delay taps in the PHY. Using these delay taps, you can control the relative placement of the clock with respect to data. Once internal calibration is complete in the PHY and the PHY passes the deserialized data, this block starts processing it. This block uses the data from the PHY to control the delay taps of the PHY. The algorithm for calibration is different for single-ended IO pins and differential IO pins. This is described in the following sections.