In the differential case, two lane outputs (both P and N) from the PHY are fed to the calibration block. The sampling of the UI is done at half the frequency of the data rate. For example, if the interface speed is 1250 Mbps then the PLL clock frequency should be 625 MHz. Thus, you are sampling each UI only once on one lane. The same UI is sampled again on another lane. The block diagram of the calibration block for differential IOs is shown in the following figure.
For differential IOs, the calibration algorithm is different from single-ended IOs. Here two lanes are fed into the Alexander bang bang detector as opposed to the single-ended algorithm. For the Alexander bang bang detector to work, one lane should be edge aligned and other lane should be center aligned. This is achieved according to the following flow chart.
As described in the flow chart, P lane is center-aligned and N lane is edge-aligned. After this, both the bitslices are considered as locked and both lanes are fed to the Alexander Bang Bang Detector for VT tracking. Depending on whether the clock is early or late, the delay is incremented or decrement for both the lanes (P and N) respectively. Once the bitslices are locked, the 8-bit N channel output is given to the RX gearbox.