Clocking Scheme for Single-Bank Design and Differential IOs - 1.0 English

• For single-bank designs, if the bank has only RX pins, only one PLL will be instantiated for that bank. This PLL will provide:
  • app_rx_clk to the application and other clocks that are used internally for RX gearbox, PHY, and calibration.
  • CLKOUTPHY to PHY within the bank.
• For single-bank designs, if the bank has only TX pins, only one PLL will be instantiated for that bank. This PLL will provide:
  • .
  • app_tx_clk to the application and other clocks which are used internally for TX gearbox and PHY.
  • CLKOUTPHY to PHY within the bank.
• For single-bank designs, if the bank has both TX and RX pins, two PLLs will be instantiated:
  • One PLL is dedicated for TX pins. This PLL provides:
    • app_tx_clk to the application and other clocks which are used internally for TX gearbox and PHY.
    • CLKOUTPHY to TX part of PHY within the bank.
  • Other PLL is dedicated for RX pins. This provides :
    • app_rx_clk to the application and other clocks which are used internally for RX gearbox, PHY, and calibration
    • CLKOUTPHY to RX part of PHY within the bank.

The following diagram shows the clocking scheme for a sample single bank design with differential IOs. This bank has both TX pins and RX pins.