- For single-ended IO designs, one XPLL per bank is instantiated if that bank has any pins (TX pins or RX pins or both).
- For two-bank or three-bank designs, bank 1 is considered as the master bank and the other banks are considered as slave banks.
- This XPLL from the master bank provides the following clocks:
-
- In a multi-bank scenario, the master bank drives the input clock of slave PLLs.
- Generates
app_tx_clk/app_rx_clkto the Versal ACAP logic and other clocks that are used internally for TX/RX gearbox ,Calibration logic, and PHY . - CLKOUTPHY to PHY within the master bank.
- The XPLL from the slave bank will drive the CLKOUTPHY to PHY within that bank.
- The following diagram shows the example clocking for a three-bank design which is based on single-ended IOs.
Figure 1. Sample Clocking Scheme for Single-Ended Three-Bank Design
