Clocking Scheme for a Three-bank Design and Differential IOs - 1.0 English

For three-bank designs, the middle bank (bank 1) is always considered as the master bank and other two are slave banks.

• If all pins in the three banks are RX, only one PLL will be instantiated for each bank.
  • The PLL in the master bank will provide:
    • Input clock for the PLL in the slave banks.
    • app_rx_clk to the application and other clocks that are used internally for RX gearbox, PHY, and Calibration.
    • CLKOUTPHY to PHY within the bank.
  • The PLL in the slave banks will provide:
    • CLKOUTPHY to PHY within the bank.
  • If all pins in the three banks are TX, only one PLL will be instantiated for each bank.
    • The PLL in the master bank will provide:
      • Input clock for the PLL in the slave banks.
      • app_tx_clk to the application and other clocks that are used internally for TX gearbox and PHY.
      • CLKOUTPHY to PHY within the bank.
    • The PLL in the slave banks will provide:
      • CLKOUTPHY to PHY within the bank.
  • If any or all of the banks have both TX and RX pins, the clocking scheme will be as follows.
    • The first PLL in the master bank will always provide:
      • Input clock for of the first PLL in the slave banks.
      • CLKOUTPHY to TX part of PHY within the bank.
      • app_tx_clk to the application and other clocks that are used internally for TX gearbox and PHY.
    • The second PLL in the master bank will always provide:
      • Input clock for the second PLL in the slave banks.
      • app_rx_clk_ to the application and the other clocks that are used internally for the RX gearbox, PHY, and calibration.
      • CLKOUTPHY to RX part of PHY within the bank.
    • The first PLL in the slave bank will provide CLKOUTPHY to TX pins in PHY if TX pins are present in the slave bank. If TX pins are not present in the slave bank then the corresponding PLL will not be instantiated.
    • The second PLL in the slave bank will provide CLKOUTPHY to RX pins in PHY if RX pins are present in the slave bank. If RX pins are not present in the slave bank then the corresponding PLL will not be instantiated.

The following diagram shows the sample clocking structure for a sample three-bank design where all the banks have both TX and RX pins.

The following diagram shows the clocking structure for a sample three-bank design. Bank 0 has only TX pins and Bank 2 has only RX pins. Because bank 0 has only TX pins, only one PLL is instantiated. Because bank 2 has only RX pins, only one PLL is instantiated. The master bank is instantiated with two PLLs.