Clocking scheme for a two bank design and Differential IOs - 1.0 English

ADC DAC Interface LogiCORE IP Product Guide (PG388)
Document ID
PG388
Release Date
2022-05-16
Version
1.0 English

For two-bank designs, one of the banks is considered as the master bank and one as the slave bank. Bank 1 is the master bank and bank 0 is the slave bank.

  • If all the pins in both the banks are RX, Only one PLL will be instantiated for each bank.
    • The PLL in the master bank will provide:
      • Input clock for the PLL in the slave bank.
      • app_rx_clk to the application and other clocks that are used internally for RX gearbox, calibration logic, and PHY.
      • CLKOUTPHY to PHY within the bank.
    • The PLL in the slave bank will provide:
      • CLKOUTPHY to PHY within the bank.
  • If all the pins in both banks are TX, only one PLL will be instantiated for each bank.
    • The PLL in the master bank will provide:
      • Input clock for the PLL in the slave bank.
      • app_tx_clk to the application and other clocks that are used internally for TX gearbox and PHY.
      • CLKOUTPHY to PHY within the bank.
    • The PLL in the slave bank will provide:
      • CLKOUTPHY to PHY within the bank.
  • If either or both of the banks has both TX and RX pins, the clocking scheme be as follows:
    • The first PLL in the master bank will always provide:
      • Input clock for the first PLL in the slave bank.
      • CLKOUTPHY to TX part of PHY within the bank.
      • app_tx_clk to the application and other clocks that are used for TX gearbox and PHY
    • The second PLL in the master bank will always provide:
      • Input clocks for the second PLL in the slave bank.
      • app_rx_clk to the application and other clocks that are used for RX gearbox, PHY and calibration.
      • CLKOUTPHY to RX part of PHY within the bank.
    • The first PLL in the slave bank will provide CLKOUTPHY to the TX pins in PHY if TX pins are present in the slave bank. If TX pins are not present in the slave bank, then the corresponding PLL will not be instantiated.
    • The second PLL in the slave bank will provide CLKOUTPHY to RX pins in PHY if RX pins are present in the slave bank. If RX pins are not present in the slave bank, then the corresponding PLL will not be instantiated.