Constraining the Core/Subsystem - 1.0 English

ADC DAC Interface LogiCORE IP Product Guide (PG388)

Document ID
PG388
Release Date
2022-05-16
Version
1.0 English

Required Constraints

This section is not applicable for this IP core or subsystem.

Device, Package, and Speed Grade Selections

This section is not applicable for this IP core or subsystem.

Clock Frequencies

This section is not applicable for this IP core or subsystem.

Clock Management

This section is not applicable for this IP core or subsystem.

Clock Placement

This section is not applicable for this IP core or subsystem.

Banking

This section is not applicable for this IP core or subsystem.

Transceiver Placement

This section is not applicable for this IP core or subsystem.

I/O Standard and Placement

The ADC DAC IP generates the appropriate I/O standards and placement based on the selections made in the Vivado IDE for the interface type and options.