Core Overview - 1.0 English

ADC DAC Interface LogiCORE IP Product Guide (PG388)

Document ID
PG388
Release Date
2022-05-16
Version
1.0 English

The ADC DAC Interface IP core provides solutions for interfacing with multiple ADCs or DACs. Each I/O bank in VersalĀ® devices contains 54 pins (nine nibbles) that can be used for input and output. This IP provides options to configure up to three banks as RX lanes or TX lanes. RX lanes aid in serial to parallel conversion and TX lanes aid in parallel to serial conversion. The core is organized in high-level blocks as follows:

Calibration and Tracking
This logic aids in centering of data for RX lanes. This logic only exists for RX and does not exist for TX lanes.
Gearbox
Gearbox logic converts the data from 4-bit data words (Single Ended) or 8-bit data words (Differential) to 12/14/16-bit data words for RX lanes. Similarly, for TX lanes gearbox logic converts the data from 12/14/16-bit data words for TX lanes to 8-bit data words.
Physical layer
The physical layer provides a high-speed interface to the ADC and DAC. This layer includes the hard blocks inside the Versal ACAP which perform the following:
  • Data serialization and transmission.
  • Data capture and deserialization.
  • High-speed clock generation and synchronization.
  • Coarse and fine delay elements per pin.
Figure 1. ADC DAC Block Diagram